1. Field of the Invention
The invention relates generally to the layout and manufacturing process of the semiconductor power devices. More particularly, this invention relates to an improved configuration of gate-to-drain (GD) clamp combined with the electrostatic discharge (ESD) protection circuit for power device breakdown protection to achieve smaller die size, reduced leakage currents, better control of the GD clamp breakdown voltage and lower production cost.
2. Description of the Prior Art
Conventional layout for manufacturing semiconductor power devices with protection circuits against breakdown and also against electrostatic discharges (ESD) still has a limitation. A general practice is to place the multiple gate-to-drain Zener diodes at the periphery of the die. These gate-to-drain Zener diodes may be made in the same way as gate-to-source ESD diodes. The configuration causes the die size to increase and therefore increases the production costs of the power devices. Another technical difficulty is related to the great width of the gate to drain Zener diode. The leakage current Idss is proportional to the width of the Zener diodes in this configuration. The great width of the Zener diodes thus makes it difficult to limit the Idss leakage current under 10 μA that is generally required in many of such power device applications.
FIG. 1 is a top view of the gate-drain clamp for the device as generally implemented in the conventional semiconductor power device. The gate to drain clamping voltage is implemented with a plurality of Zener diodes 110 on the periphery of the device. The multiple Zener diodes as shown thus occupy large areas of the die. Furthermore, as discussed above, the Zener diodes formed around all the peripheral edges have a very large width thus causing the drain-source leakage Idss current to increase significantly and adversely affect the performance rating of the clamping circuits.
The function of a gate-to-drain (GD) clamp is to work with a gate resistor to turn on the FET before the drain to source voltage reaches avalanche breakdown that can potentially cause permanent damage to FET. The GD clamp function as disclosed by U.S. Pat. No. 5,365,099 is implemented with back-to-back polysilicon diodes alone. The back-to-back polysilicon diodes are usually made as alternating P and N stripes. However, such device has a drawback that the polysilicon diodes occupy too much space wherein each stripe has a width of approximately five microns for protecting a breakdown voltage up to six volts.
Shen et al. disclose in U.S. Pat. No. 5,536,958 a semiconductor device that has an improved high voltage protection by including an integrated Schottky diode in conjunction with a plurality of back-to-back polysilicon diodes to limit the voltage potential that may arise between the gate and the drain terminal. In another embodiment of U.S. Pat. No. 5,536,958, a contact region is formed in the substrate rather than a Schottky diode to contact the back-to-back diodes to support some of the voltage with a pinch-off effect with the remainder of the voltage supported by the substrate. The structure is able to support excessive voltage in the conduction mode rather than the avalanche mode. Furthermore, in the 5th International Symposium of Power Semiconductor Device and IC in May, 1993, Yamazaki et al. disclose an over voltage protection circuit by integrating a silicon avalanche diode with an insulated-gate bipolar transistor (IGBT) structure that further includes a polysilicon Zener diode. With polysilicon diodes combined with Schottky diode or silicon diodes in these disclosures however the devices are limited to high breakdown voltage applications. Furthermore, the breakdown voltage for these types of clamping devices is difficult to control. Therefore, the GD clamping functions for device with low, well-controlled breakdown voltage applications with silicon diodes to supplement the back-to-back polysilicon diodes with space efficient configurations are still not available. Another problem with the prior art methods of GD clamping is that the breakdown voltage at the ends of the silicon diodes have lower breakdown voltage (BV) than the rest of the silicon diode regions. This will adversely affect the performance of the GD clamping by allowing current flow before the desired BV. The lowered BV is due to the higher electric fields that are present at the ends of P-N junctions.
A GD clamp comprising of polysilicon diodes alone occupies too much space. A conventional GD clamp comprising polysilicon diodes supplemented with a silicon or Schottky diode as disclosed in the prior art has difficulties in controlling the breakdown voltage. Therefore, it is necessary to provide an improved layout for the ESD and the gate-drain clamping circuits on the semiconductor power device such that the above discussed difficulties and limitations can be overcome.